Field
The disclosure relates generally to a current digital-to-analog converter circuit, and, more particularly, an apparatus of an exponential current digital-to-analog converter (IDAC) using a binary-weighted MSB to efficiently drive current controlled light emitting diode (LED) devices. The definition of the apparatus involves defining an exponential LSB and exponential MSB current mirrors according to a defined methodology for an exponential current digital-to-analog converter (IDAC) having improved accuracy using a binary-weighted most significant bit (MSB) and a method thereof.
Description of the Related Art
Light emitting diode (LED) device brightness control is achieved by controlling the current that passes through the LED device. In order to dim LED device with less power dissipation than current control, a method of power control is used known as pulse width modulation (PWM). By varying the average current across the LED device, the device can be made to appear dimmer, or brighter. The brightness of current controlled light emitting sources is substantially proportional to the current flowing in them. Because of this characteristic, a digital-to-analog current converter (IDAC) is commonly used to control the brightness of visual displays.
Using a sole linear current digital-to-analog solution has the disadvantage of being perceived by human visual perception as a non-linear dimming process. Therefore a current source that is exponentially related to digital inputs, such as an exponential IDAC, is needed to maintain uniformity in changes to the level of the display brightness.
It is a common practice, the IDAC exponential characteristic is separated into a least significant bit (LSB) and most significant bit (MSB) parts as necessary to contain the circuit complexity and reduce the silicon area. The LSB generates an exponential current with a DNLLSB and so does the MSB with a DNLMSB 
As discussed in published U.S. Pat. No. 7,132,966 to Adler et al., a circuit to convert a floating point number into an analog current is discussed. The conversion is performed directly by using an exponential current digital-to-analog converter (e.g. exponential IDAC) and a cascaded linear current digital-to-analog converter (e.g. linear DAC).
As discussed in published U.S. Pat. No. 7,038,402 to Adler et al., a circuit to achieve linear and exponential control over current to drive color LEDs is shown. A method for convert floating point number into an analog current is discussed. The conversion is performed directly by using an exponential current digital-to-analog converter (e.g. exponential IDAC) and a cascaded linear current digital-to-analog converter (e.g. linear DAC) to drive color LEDS, and preferably red, green, blue (RGB) LEDs.
As discussed in published U.S. Pat. No. 8,421,659 to von Staudt et al., discloses circuits using a digital-to-analog converter (DAC) controlled by a state machine to produce an analog output that is within a least significant bit (LSB) of a digital input bits. Trim solutions are proposed for major transitions of the digital bits.
As discussed in published U.S. Patent Application US 2011/0057825 to Marraccini et al., discloses systems to achieve logarithmic digital-to-analog converter (DAC). The logarithmic DAC is a linear DAC whose output voltage is converted into a logarithmic current value directly from an I-V characteristics of a diode element. The patent application utilizes a diode in the network to establish the voltage-current transformation.
As illustrated in FIG. 1, an IDAC architecture is shown. In the implementation of FIG. 1, there is a LSB network that separates the LSB base current Io and the exponential part ILSB_exp. In the implementation of FIG. 1, there is a MSB network that separates the MSB base current To and the exponential part IMSB_exp. FIG. 1 shows a power pad VDD 1, a ground rail VSS 2, a VIDAC_FB pad 3, a first PFET current mirror (20 and 21), a second PFET current mirror (30 and 31), a LSB network 40, and a MSB network 50, a buffer element 60, a transistor 70, and output transistor 80. The LSB network 40 contains a LSB diode 41, a transistor 42 for the base current Io, a variable transistor 43 for the exponent term ILSB_exp, and a LSB responsive switch 44. The MSB network 50 contains a MSB diode 51, a variable transistor 52 for the exponent term ILSB_exp, and a MSB responsive switch 54. Implementing equation for low differential non-linearity (DNL) values using one LSBdiode is feasible task to undertake, considering that at the first part of the characteristic is at relatively low currents and the exponential characteristic is easily approximated with a linear function plus correction terms. But, the difficulty is in the defining of the MSB. Implementing an equation becomes quite tricky if DNLMSB is an irrational number, because that means synthesizing and implementing an MSB current mirror at high currents with an irrational gain. The only way to approximate an irrational gain is to implement several diodes with different gains within the MSB. Systematic error will occur in the overall IDAC DNL. Furthermore, matching between the different branches to contribute to the DNLMSB will be not achievable due to the different plurality of elements of different sizes (e.g. diode elements). These design challenges can easily turn a low DNL exponential IDAC into a high complexity, unmanageable design. In the attempt to simplify matters and to contain the expense of silicon area, a technique called “dithering” is being commonly used. This consists in targeting the design for higher differential non-linearity (DNL) for then getting lower DNL by switching the digital input between two consecutive codes, using an appropriate frequency and duty cycle. The dithering usually creates more issues than it was meant to solve, as it requires good dynamic performance by a structure that is inherently slow, being made of several big current mirrors. Furthermore, it doesn't resolve the problem of having an irrational MSB gain, and so a low DNL accuracy, if a proper architecture wasn't chosen in the first place.
As illustrated in FIG. 2, a high level diagram of a system to drive light emitting diode (LED) devices is shown. The block diagram shows a system 100, to drive a string of LED elements. The system contains a power output pad 101, a ground connection 102, an output bondpad 103, a error amplifier 110, a pulse width modulation (PWM) comparator 120, a DC-DC converter 130, a series configured LED elements 140 to 141, a current source 150. The PWM used in the PWM comparator is not to be confused with the PWM used for dimming LEDs as noted in the prior discussion and description of FIG. 1. The IDAC that provides current control for the LEDs used in portable displays needs to be low voltage compliance to reduce the system power loss, so vital for the battery life. The lower the system is able to regulate the node VIDAC_FB the better the efficiency of the system. In the architecture shown in FIG. 1, the operating point of the MSB stage is set by the MSB diode branch, so if VIDAC_FB goes below the drain voltage saturation, VDsat, of the MSB diode device (referred to as IDAC voltage compliance) the current accuracy will be heavily affected. The IDAC voltage compliance (VDsat) is inversely proportional to the size of the MSB output devices. This means that to get good efficiency performance in driving the LEDs, area must be spent in designing the MSB. If the MSB is already large and complex to meet the DNL specification, it will be very difficult to meet the low voltage compliance requirement as well, which is inversely proportional to the MSB devices size. Also considering that different branches with different diodes, so different VDsat, are involved in generating the final output current. So it might not be possible to simply increase the MSB size to push the output voltage VOUT further down without squeezing some current branches. The voltage drop from the transistor NOUT also impacts the system efficiency. The system efficiency can be written as
  η  =            P      OUT              P      IN      where POUT is the output power, and PIN is the input power. The output power can be defined as a function of IDAC, as follows:POUT=(Vout−VIDAC_FB)*IDACTo maximize the efficiency is mandatory to reduce the loss in the system. The first visible loss affecting the efficiency of the system is the voltage VIDAC_FB required to obtain the desired current. It's evident that current accuracy and efficiency are in contrast, as to get better efficiency we need to push VIDAC_FB down as much as possible but if we go further down than VDsat we will lose current accuracy.
In these prior art embodiments, the solution to design a low differential non-linearity (DNL) and low voltage compliant exponential digital-to-analog converter (IDAC) that minimizes architectural complexity and mismatch variations is not achieved.